Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-11-20
2007-11-20
Smoot, Stephen W. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000
Reexamination Certificate
active
10942555
ABSTRACT:
Novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via; etching a trench in the second dielectric layer; and filling the trench with a conductive metal such as copper. In another embodiment, the method includes providing a dielectric layer on a substrate; etching a partial via in the dielectric layer; etching a partial trench in the dielectric layer over the partial via; completing the via and the trench in a single etching step; and filling the via and the trench with a conductive metal such as copper to complete the via and metal line, respectively.
REFERENCES:
patent: 5926732 (1999-07-01), Matsuura
patent: 6204168 (2001-03-01), Naik et al.
patent: 6211069 (2001-04-01), Hu et al.
patent: 6287960 (2001-09-01), Lao
patent: 6350682 (2002-02-01), Liao
Smoot Stephen W.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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