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Area efficient memory architecture with decoder self test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Area efficient parallel turbo decoding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Area optimized edge-triggered flip-flop for high-speed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Area-efficient convolutional decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Area-efficient surviving paths unit for Viterbi decoders

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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Arithmetic built-in self-test of multiple scan-based...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Arithmetic circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Arithmetic operation method for cyclic redundancy check and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Arithmetic unit performing cyclic redundancy check at high...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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ARQ combining holdoff system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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ARQ for point to point links

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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ARQ for point to point links

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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ARQ for point to point links

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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ARQ for point to point links

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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ARQ method for wireless communication

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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ARQ method with adaptive transmittal data block positions

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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ARQ method with adaptive transmittal data block positions

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Arrangement and method of testing an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Arrangement and method of testing an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Arrangement for fault detection in circuit interconnections

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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