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On-chip circuitry for bus validation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip comparison and response collection tools and techniques

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip debugger

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip design for monitor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip detection of clock gitches by examination of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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On-chip error detection and correction system for an...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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On-chip failure analysis circuit and on-chip failure...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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On-chip high-speed serial data analyzers, systems, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip high-speed serial data analyzers, systems, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip interface trap characterization and monitoring

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip jitter testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip method and apparatus for testing semiconductor circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip receiver eye finder circuit for high-speed serial link

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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On-chip receiver sensitivity test mechanism

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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On-chip receiver sensitivity test mechanism

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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On-chip sampling circuit and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip sampling circuit and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip sampling circuit and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip sampling circuit and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip scan clock generator for ASIC testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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