On-chip sampling circuit and method

Details On-chip sampling circuit and method On-chip sampling circuit and method

2007-07-31

2007-07-31

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000, C714S734000, C703S028000, C324S754090, C365S201000

Reexamination Certificate

active

11109535

ABSTRACT:
Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout.

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Mehrdad Nourani, Detecting Signal-Overshoots for Reliability Analysis in High-Speed System-on-Chips, IEEE Transactions on Reliability, Dec. 2002, pp. 494-504, vol. 51, No. 4.

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