On-chip sampling circuit and method

Details On-chip sampling circuit and method On-chip sampling circuit and method

2008-07-22

2008-07-22

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S030000, C714S045000, C714S723000, C714S734000, C714S718000, C324S754090, C324S756010, C324S757020, C702S118000

Reexamination Certificate

active

07404124

ABSTRACT:
Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

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Nourani, Mehrdad et al., “Detecting Signal-Overshoots for Reliability Analysis in High-Speed System-on-Chips,” IEEE Transactions on Reliability, vol. 51, No. 4, pp. 494-504, Dec. 2002.

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