On-chip interface trap characterization and monitoring

Details On-chip interface trap characterization and monitoring On-chip interface trap characterization and monitoring

2005-05-31

2008-12-30

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S735000, C438S234000

Reexamination Certificate

active

07472322

ABSTRACT:
A method and apparatus for testing semiconductor wafers is disclosed in which a test circuit is used that includes a waveform generator. The test circuit can test a single transistor or can test multiple transistors. A testing method is disclosed in which a supply voltage is applied to the waveform generator to produce pulses that are applied to the gate of a transistor to be tested. A bias voltage is applied to the source and drain of the transistor to be tested, and the charge pumping current that is generated at the substrate is then measured. The process can be repeated at different bias voltage levels to obtain additional current measurements, indicating the maximum charge pumping current for the transistor that is being tested. The determined maximum charge pumping current can then be used for determining whether there is excessive 1/f noise in the device under test.

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