On-chip circuitry for bus validation

Details On-chip circuitry for bus validation On-chip circuitry for bus validation

2005-01-24

2009-10-27

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S043000, C714S056000, C714S715000, C714S738000, C714S739000

Reexamination Certificate

active

07610526

ABSTRACT:
Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus, the bus being connectable to an external device configured to drive one or more electrical signals onto the bus. The integrated circuit may comprise a first logic configured to receive a test sequence of electrical signals from the bus, a second logic configured to produce a check sequence of electrical signals related to the test sequence of electrical signals, and a compare logic operably connected to the first logic and the second logic. The compare logic may be configured to determine whether the bus is correctly transmitting data based, at least in part, on comparing the test sequence and the check sequence.

REFERENCES:
patent: 5228042 (1993-07-01), Gauthier et al.
patent: 6292911 (2001-09-01), Swanson
patent: 6609221 (2003-08-01), Coyle et al.
patent: 7047458 (2006-05-01), Nejedlo et al.
patent: 5-322987 (1993-12-01), None
patent: 2000-88927 (2000-03-01), None
patent: 2000-181811 (2000-06-01), None
patent: 2000-194608 (2000-07-01), None
patent: 2001-85622 (2001-03-01), None
patent: 2001-267425 (2001-09-01), None
patent: 2003-173268 (2003-06-01), None
patent: 2003-173362 (2003-06-01), None
patent: 2004-94451 (2004-03-01), None
patent: 2004355435 (2004-12-01), None
patent: WO 00/73809 (2000-12-01), None
Machine generated English translation of Sony Corp. JP 2000-88927, 14 pages, from the JPO website.
Patent Office—China, Office Action dated Jul. 4, 2008, for Application No. 200610006876.2; pp. 1-10.
English translation of Japan Office Action dated Feb. 17, 2009, 4 pages.

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