On-chip jitter testing

Details On-chip jitter testing On-chip jitter testing

2002-12-26

2008-08-05

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S055000

Reexamination Certificate

active

07409621

ABSTRACT:
On-chip jitter testing includes providing a clock signal to a circuit under test and delaying outputs from the circuit under test by predetermined delay values. For each delay value, a corresponding output from the circuit under test is compared with a reference signal derived from the clock signal to produce a bit error rate count for each delay value. A jitter value in the output of the circuit under test is determined based on the bit error rate counts.

REFERENCES:
patent: 4164648 (1979-08-01), Chu
patent: 5489466 (1996-02-01), Inaba et al.
patent: 5590341 (1996-12-01), Matter
patent: 5663991 (1997-09-01), Kelkar et al.
patent: 5703838 (1997-12-01), Gorbics et al.
patent: 5793822 (1998-08-01), Anderson et al.
patent: 6295315 (2001-09-01), Frisch et al.
patent: 6421794 (2002-07-01), Chen et al.
patent: 6448754 (2002-09-01), Ihs et al.
patent: 6657467 (2003-12-01), Seki et al.
patent: 6670800 (2003-12-01), Beach et al.
patent: 6747470 (2004-06-01), Muhtaroglu et al.
patent: 6777921 (2004-08-01), Abdennadher et al.
patent: 6836872 (2004-12-01), Abdennadher
patent: 6822491 (2005-03-01), Fattouh et al.
patent: 6868534 (2005-03-01), Fattouh et al.
patent: 6934307 (2005-08-01), DeCusatis et al.
patent: 2002/0190283 (2002-12-01), Seno
patent: 2003/0112027 (2003-06-01), Muhtaroglu et al.
patent: 2003/0141859 (2003-07-01), Abdennadher et al.
patent: 2003/0177427 (2003-09-01), Fattouh et al.
patent: 2003/0210028 (2003-11-01), Beach et al.
patent: 2004/0060017 (2004-03-01), Abdennadher
patent: 2004/0085085 (2004-05-01), Muhtaroglu et al.
Sunter et al., BIST for phase-locked loops in digital applications, International Test Conference, Proceedings, Sep. 28-30, 1999, pp. 532-540.
Abdennadher, Salem, et al., “Mixed Signal DFT/BIST Automation Using Behavioral Modeling”, 2001 Southwest Symposium on Mixed-Signal Design (SSMSD), pp. 137-140 (Feb. 25-27, 2001).
Arabi, Karim, et al., “Digital Oscillation-Test Method for Delay and Stuck-at Fault Testing of Digital Circuits”, International Test Conference, pp. 91-100 (1998).
Arabi, K., et al., “Dynamic Digital Integrated Circuit Testing Using Oscillation-Test Method”, Electronics Letters, vol. 34, No 8, pp. 762-764 (Apr. 16, 1998).
Abdennadher, Salem, “Flow for Phase Locked Loop Mixed Signal Simulation and Characterization Using Behavioral Modeling”, 2003 Southwest Symposium on Mixed-Signal Design (SSMSD), pp. 66-70 (Feb. 23-25, 2003).
Dufaza, C., et al., “Boolean Equations for Multiple Paths Sensitisation of Digital Oscillation Built-In Self Test”, Electronics Letters, vol. 34, No. 23, p. 2213-2215 (Nov. 12, 1998).
U.S. Appl. No. 11/240,687, entitled “Supply Voltage Characteristic Measurement”, filed Sep. 30, 2005, by Horst W. Wagner.
Desai, Utpal, et al., “Itanium Processor Clock Design”, Proceedings of the 2000 International Symposium on Phyical Design (ISPD), pp. 94-98 (May 2000).
Takamiya, Makoto, et al., “An On-chip 100GHz-Sampling Rate 8-channel Sampling Oscilloscope with Embedded Sampling Clock Generator”, 2002 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, vol. I, pp. 182-1 83 & 458 (Feb. 3, 7, 2002).
Takamiya, Makoto, et al., “An On-chip 100GHz-Sampling 8-channel Sampling Oscilloscope with Embedded Sampling Clock Generator”, 2002 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, vol. 2, pp. 140-141 & 439 (Feb. 3-7, 2002).

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