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Testing of ECC memories

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Testing of electronic circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing of high speed DDR interface using single clock edge...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing of integrated circuit devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing of integrated circuit devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing of integrated circuit receivers

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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Testing of integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing of integrated circuits using boundary scan

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing of modules operating with different characteristics...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing of replicated components of electronic device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing propagation delay of a shift register using a ring...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing regularly structured logic circuits in integrated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing replicated sub-systems in a yield-enhancing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing self-repairing memory of a device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Testing self-repairing memory of a device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Testing synchronization circuitry using digital simulation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing system and method of using same

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Testing system and methods with protocol pattern injection...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing system for a device under test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Testing system for circuit board self-test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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