Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2004-01-28
2008-08-05
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S765010
Reexamination Certificate
active
07409612
ABSTRACT:
An integrated circuit with a test interface contains a boundary scan chain with cells (14) coupled between a test data input (TDI) and output (TDO) in a shift register structure. Each cell (14) is also coupled between a respective one of the terminals (16) and the core circuit (10). A test control circuit (TAP_C) supports an instruction to switch the boundary scan chain to a mode in which mode selectable first ones of the cells (14) transport data serially along the boundary scan chain while selectable second ones of the cells (14) write or read data that has been or will be transported through the first ones of the cells (14) in the further mode to or from the terminals (16) from or to the scan chain.
REFERENCES:
patent: 6343358 (2002-01-01), Jaggar et al.
patent: 6862705 (2005-03-01), Nesbitt et al.
patent: 6886122 (2005-04-01), Barthel
patent: 6961884 (2005-11-01), Draper
patent: 7000163 (2006-02-01), Dirks et al.
Vranken H et al: “Enhanced Reduced Pin-Count Test for Full-Scan Design” ITC International Test Conference, vol. 18, No. 2, Oct. 30, 2001 pp. 738-474.
Van De Logt Leon Maria Albertus
Van Der Heyden Frank
Waayers Thomas Franciscus
Britt Cynthia
NXP B.V.
Zawilski Peter
LandOfFree
Testing of integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Testing of integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testing of integrated circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4013300