Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-01
2007-05-01
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S731000, C326S096000
Reexamination Certificate
active
10710451
ABSTRACT:
Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules operate with different characteristics of a control signal. In an embodiment, another module (“subsystem module”) may be implemented to be tested with any of a multiple characteristics of a control signal, and a register which is programmable to generate a derived control signal of a desired characteristic from an original control signal, is provided. The derived control signal is provided to test the subsystem module. According to an aspect of the invention the desired characteristic may be determined, for example, to test a path between the two modules at the same speed as at which the path would be operated in a functional mode.
REFERENCES:
patent: 6742151 (2004-05-01), Park et al.
patent: 6744285 (2004-06-01), Mangum et al.
Krishnamoorthy Nikila
Parekhji Rubin Ajit
Saha Anindya
Lamarre Guy
Shaw Steven A.
Tabone, Jr. John J.
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