Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-08-28
2007-08-28
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S742000
Reexamination Certificate
active
11162595
ABSTRACT:
A multi-processor chip has several processor cores that are simultaneously tested in parallel. The processor cores each have identical scan chains that produce identical test results absent defects. Expected test data is scanned from an external tester onto the chip and replicated to each processor core's scan chain. The expected test data is compared to scan chain outputs at each processor core. Any mismatches set a test-fail bit for that processor core. Each processor core has repairable scan chains and a separate critical scan chain. Failures in the critical scan chain in any processor core cause the whole chip to fail. Processor cores are disabled that have failures in their repairable scan chains, allowing the chip to be repairable by using the remaining processor cores. Critical scan chains include logic that drives to other blocks on the chip, while repairable scan chains have logic embedded deep within a processor core.
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Makar Samy R.
Patkar Niteen A.
Auvinen Stuart T.
Azul Systems, Inc
Britt Cynthia
g Patent LLC
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