Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-08-20
2008-07-15
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S733000
Reexamination Certificate
active
07401271
ABSTRACT:
A testing system (and method of using same) for testing a system-under-test (SUT) are provided. One embodiment of the testing system includes first, second, and third logic sections. The third logic section selectively couples either the first logic section or the second logic section to the SUT, based upon two control signals transmitted to the third logic section. One of the control signals is transmitted from a source external to the SUT, first logic section, second logic section, and third logic section. The other control signal is transmitted from the first logic section. When the third logic section couples the first logic section to the SUT, the first logic section may transmit one or more test-related signals to the SUT. When the third logic section couples the second logic section to the SUT, the second logic section may transmit one or more other signals to the SUT.
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Britt Cynthia
EMC Corporation
Krishnendu Gupta
Ouellette Scott A.
Tabone, Jr. John J
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