Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-09-05
2006-09-05
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S819000, C713S401000
Reexamination Certificate
active
07103815
ABSTRACT:
An integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The delay circuit receives the testing output signal at a first clock rate internal to the integrated circuit device and compares test data in the testing output signal to expected test signal values. The delay circuit provides a result to an external connector at a second clock rate that is slower than the first clock rate.
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Ho Fan
Ong Adrian E.
Inapac Technology, Inc.
Sidley Austin LLP
Tu Christine T.
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