LandOfFree - US Patents - Listing for Error detection/correction and fault detection/recovery,Pulse or data error handling

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

SRAM that can be clocked on either clock phase

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

SRAM-compatible memory for correcting invalid output data...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

SSD test systems and methods

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Stability test for silicon on insulator SRAM memory cells...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Star-I: scalable tester architecture with I-cached SIMD technolo

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

STAR-I: scalable tester architecture with I-cached SIMD technolo

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Start/stop circuit for performance counter

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Start/stop circuit for performance counter

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

State metric memory of viterbi decoder and its decoding method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

State relaxation based subsequence removal method for fast stati

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

States encoding in multi-bit flash cells for optimizing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Static random access memory (SRAM) unit and method for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Static semiconductor memory device having test mode

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Static test sequence compaction using two-phase restoration and

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Static timing analysis approach for multi-clock domain designs

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Static viterbi detector for channels utilizing a code having...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Statistical decision system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Statistical yield of a system-on-a-chip

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique

Statistics signature generation and analysis