Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-07-17
2007-07-17
Torres, Joseph D. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S718000, C365S201000, C365S200000
Reexamination Certificate
active
10885993
ABSTRACT:
A static random access memory (SRAM) unit is provided having a read control module, a write control module, and a bypass. The read control module is configured to communicate a read signal defined to read from a first address in the SRAM unit. The write control module is configured to communicate a write signal defined to write to a second address in the SRAM unit. The bypass is disposed to connect the write control module to the read control module. The bypass is further configured to prevent a simultaneous communication of the read signal and the write signal when the first address and the second address are equivalent.
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