Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-03-08
2011-03-08
Tu, Christine T (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S745000, C365S200000, C365S201000
Reexamination Certificate
active
07904766
ABSTRACT:
Improving statistical yield of a system-on-a-chip. The system-on-a-chip includes several memory systems. Each memory system includes a large number of memories. The memories are tested to identify any faulty memories. One or more margins of the faulty memories are then varied and the memories are then tested again.
REFERENCES:
patent: 5034923 (1991-07-01), Kuo et al.
patent: 5337318 (1994-08-01), Tsukakoshi et al.
patent: 5488578 (1996-01-01), Yamada
patent: 6453433 (2002-09-01), Vollrath
Behera Niranjan
Shubat Alexander
Evergreen Valley Law Group P.C.
Radhakrishnan Kanika
Synopsys Inc.
Tu Christine T
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