States encoding in multi-bit flash cells for optimizing...

Details States encoding in multi-bit flash cells for optimizing... States encoding in multi-bit flash cells for optimizing...

2007-10-25

2011-11-08

Abraham, Esaw (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C365S185240, C365S185330

Reexamination Certificate

active

08055972

ABSTRACT:
Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2M−1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

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EPO, “Supplementary European search report,” corresponding European Patent Application No. 05 70 9145.6, mailed on Feb. 14, 2011, 3 pages.

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