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Scan output connection in tap and scan test port

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan path adaptor with state machine, counter, and gate...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan path circuit and semiconductor integrated circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan path circuit and semiconductor integrated circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan path circuit and semiconductor integrated circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan path circuit having a selection circuit for delivering...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan path circuit permitting transition between first and second

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan path circuitry for programming a variable clock pulse width

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan path circuitry including a programmable delay circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan path test support

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan register and methods of using the same

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan sequenced power-on initialization

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan stream sequencing for testing integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan stream sequencing for testing integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan string segmentation for digital test compression

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan string segmentation for digital test compression

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan structure for CMOS storage elements

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan structure for improving transition fault coverage and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan test circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan test circuit and scan test control method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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