Scan register and methods of using the same

Details Scan register and methods of using the same Scan register and methods of using the same

2005-01-07

2008-11-25

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

07457998

ABSTRACT:
An improved scan register and methods of using the same have been disclosed. In one embodiment, the improved scan register includes a master latch having a data input, a data output, and a control input. The control input is coupled to a clock signal. The master latch is operable to store data. The improved scan register further includes a scan latch having a data input, a data output, and a control input. The data input of the scan latch is coupled to the data output of the master latch. The scan latch is operable to receive and to store the data from the master latch in response to the scan latch being in a scan mode. The improved scan register may further include a functional latch having a data input, a data output, and a control input. The data input of the functional latch is coupled to the data output of the master latch. The functional latch is operable to receive and to store the data from the master latch in response to the functional latch being in a functional mode. Other embodiments have been claimed and described.

REFERENCES:
patent: 6785855 (2004-08-01), Zhang et al.
patent: 7246287 (2007-07-01), Chua-Eoan et al.
SAVIR, “Scan Latch Design for Delay Test”, International Test Conference, 1997 IEEE, pp. 19.2, pp. 446-453.
Sankaralingam et al., “Inserting Test Points to Control Peak Power During Scan Testing”, Proceedings of the 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002, IEEE, 9 pages.
Gerstendorfer et al., “Minimized Power Consumption for Scan-Based Bist”, ITC International Test Conference, Paper 4.1, 1999 IEEE, pp. 77-84.
Huang et al., “Reduction of Power Consumption in Scan-Based Circuits during Test Application by an Input Control Technique”, 2001 IEEE, vol. 20, No. 7, pp. 911-917.
Dervisoglu et al., “Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement”, International Test Conference, 1991 IEEE, Paper 14.1, pp. 365-374.
Abramovici et al., “Digital Systems Testing and Testable Design”, Design for Testability, IEEE Press, 1990, pp. 358-417.

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