Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-08-23
2008-08-12
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07412636
ABSTRACT:
One may use a new technique to determine the placement of exclusive-ors in each scan string of a chip may achieve improved test vector compression, and one may combine this technique with methods to minimize the overhead of the exclusive-or logic, to eliminate clock enable logic for multiple scan strings, to minimize the changes to existing test logic insertion and scan strings reordering, and to minimize the test vector compression computation time.
REFERENCES:
patent: 6378108 (2002-04-01), Schoellkopf
patent: 2005/0216805 (2005-09-01), Guettaf
Connolly Bove & Lodge & Hutz LLP
Kerveros James C
OC Applications Research LLC
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