Scan path circuit having a selection circuit for delivering...

Details Scan path circuit having a selection circuit for delivering... Scan path circuit having a selection circuit for delivering...

2007-10-02

2007-10-02

Lamarre, Guy (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000

Reexamination Certificate

active

10265613

ABSTRACT:
A scan path circuit having a plurality of scan chain circuits includes a data compression circuit for data-compressing the outputs of the scan chain circuits and delivering the compressed outputs, and a selection circuit for switching the inputs of the scan chain circuits. The selection circuit switches an operation mode selectively in accordance with a predetermined control signal in such a manner that, in a first operation mode, an input signal obtained from a predetermined input terminal is delivered to the first and second scan chain circuits, and in a second operation mode, the input signal is delivered to the first and third scan chain circuits. Accordingly, the logic circuit can be tested with certainty in a short required time by the simplified structure.

REFERENCES:
patent: 6158032 (2000-12-01), Currier et al.
patent: 6671838 (2003-12-01), Koprowski et al.
patent: 6715105 (2004-03-01), Rearick
patent: 6795944 (2004-09-01), Barnhart
patent: 6829740 (2004-12-01), Rajski et al.

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