Scan path circuitry including a programmable delay circuit

Details Scan path circuitry including a programmable delay circuit Scan path circuitry including a programmable delay circuit

1998-07-21

2001-09-04

Chung, Phung M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000, C714S725000

Reexamination Certificate

active

06286118

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to test mode features for integrated circuits. More particularly, the present invention relates scan path test mode features for synchronous and pipelined memories.
2. Background
It has become increasingly important to build test circuitry into integrated circuits. Scan path and Built-In Self-Test (BIST) techniques have been developed to verify the proper logic function of integrated circuits, and are valuable tools for testing the logical operation of circuits within an integrated circuit. These techniques have also been used to test or monitor the state of circuit nodes that may be otherwise inaccessible from external pins of the integrated device.
Some logic failures may be due to internal timing problems or skews within a device. If these timings can be altered, a previously inoperative part may be fixed or altered to function correctly. Additionally, the function of particular circuits or the entire integrated circuit may be characterized in response to adjusting timing parameters within the device. It also may be advantageous to adjust internal timing parameters to increase the speed of a particular circuit or the overall response of the integrated circuit. Current scan path and BIST techniques, however, are not conventionally used to programmably alter the internal timing of circuits. Therefore, what is needed is a means for altering the internal timing of signals of circuits to more accurately determine the cause of failures within the device, to improve characterization of circuit or device responses, or to increase (or decrease) the response of a device.
Scan path and BIST techniques have also been used in memory devices such as asynchronous static random access memory (SRAM) devices to test the integrity of the memory core. Synchronous SRAMs, and especially synchronous pipelined SRAMs, present particularly difficult problems of test observability and characterization.
FIG. 1
shows a conventional synchronous pipelined SRAM
100
having an asynchronous memory core
104
, clocked input register
102
and clocked output register
106
. Data or address information is clocked into input register
102
and is subsequently provided to memory core
104
. Similarly, data output from memory core
104
is clocked into and out of register
106
.
When testing memory core
104
only the output of output register
106
can be monitored. Output register
106
prevents the observation of (or “masks”) internal memory signal transients from memory core
104
. If memory core
104
is malfunctioning, then it is possible that output register
106
could mask this error by erroneously outputting expected data. Therefore, it may be difficult to determine whether output register
106
or memory core
104
is defective.
Therefore, what is needed is a means for disabling the clocked output register in a synchronous SRAM device to increase the test observability of the memory core, to directly monitor signals output by memory core
104
and/or to increase the likelihood of determining whether failures are being caused by defective memory locations or by the clocked output register.
Synchronous or pipelined memories often use clock signals for timing certain functions associated with the memory core. Incorrectly designed, manufactured, or margined time settings in these clock signals may cause failures to be observed at output register
106
even though the memory core itself is functioning properly. For example, if a sense amplifier circuit is prematurely enabled to read out data from the memory core, output register
106
may clock out incorrect data.
Therefore, what is needed is a means to disable output register
106
to monitor directly the effects of internal clock signals on the memory core. What is also needed is a means to alter the timing of internal clock signals to determine whether any failures are the result of improper signal timing or a defective memory core.
SUMMARY OF THE INVENTION
In one embodiment, the present invention concerns a circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.


REFERENCES:
patent: 4272832 (1981-06-01), Ito
patent: 4286174 (1981-08-01), Dingwall
patent: 4355377 (1982-10-01), Sud et al.
patent: 4767947 (1988-08-01), Shah
patent: 4774516 (1988-09-01), Henri et al.
patent: 4797585 (1989-01-01), Segawa et al.
patent: 4843255 (1989-06-01), Stuebing
patent: 4894791 (1990-01-01), Jiang et al.
patent: 4951254 (1990-08-01), Ontrop et al.
patent: 4985643 (1991-01-01), Proebsting
patent: 4995039 (1991-02-01), Sakashita et al.
patent: 5003513 (1991-03-01), Porter et al.
patent: 5039875 (1991-08-01), Chang
patent: 5130568 (1992-07-01), Miller et al.
patent: 5151614 (1992-09-01), Yamazaki et al.
patent: 5163168 (1992-11-01), Hirano et al.
patent: 5172012 (1992-12-01), Ueda
patent: 5177375 (1993-01-01), Ogawa et al.
patent: 5218237 (1993-06-01), Mao
patent: 5237244 (1993-08-01), DeLisle et al.
patent: 5306958 (1994-04-01), Reddy et al.
patent: 5321317 (1994-06-01), Pascucci et al.
patent: 5325367 (1994-06-01), Dekker et al.
patent: 5343082 (1994-08-01), Han et al.
patent: 5384737 (1995-01-01), Childs
patent: 5396110 (1995-03-01), Houston
patent: 5406566 (1995-04-01), Obara
patent: 5420467 (1995-05-01), Huott et al.
patent: 5428311 (1995-06-01), McClure
patent: 5438550 (1995-08-01), Kim
patent: 5590089 (1996-12-01), Roohparvar
patent: 5654988 (1997-08-01), Heyward et al.
patent: 5936977 (1999-08-01), Churchill et al.
patent: 6085498 (1985-05-01), None
patent: 6261215 (1987-11-01), None
patent: 4129416 (1992-04-01), None
patent: 5206797 (1993-08-01), None
Bonges,III et al., “A 576K 3.5-ns Access BiCMOS ECL Static RAM with Array Built-in Self Test”, 1992 IEEE, pp. 649-656.
Chappell et al., A 2-ns Cycle, 3.8-ns Access 512-kb CMOS ECL SRAM with a Fully Pipelined Architecture, Nov. 1991, IEEE Journal of Solid-State Circuits, vol. 26, No. 11, pp. 1577-1585.
Childs et al., “An 18-ns 4K×4 CMOS SRAM”, Oct. 1984, IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 545-551.
D. Roy Chowdhury, et al., “Cellular automata based pattern generator for testing RAM”, IEE Proceedings-E. vol. 139. No. 6. Nov. 1992, pp. 469-476.
David DiMarco, et al., “FA 9.8: A 200MHz 256kB Second-Level Cache with 1.6GB/s Data Bandwidth” 1996 IEEE International Solid-State Circuits Conference, ISSCC96/Session 9/SRAM/Paper FA 9.8, Feb. 9, 1996.
G. M. Ettinger, et al., “Memory-based logic sequence generation”, Microprocessors and Microsystems, vol. 9, No. 9, Nov. 1985, pp. 446-451.
Flannagan et al., “Two 13-ns 64K CMOS SRAM's with Very Low Active Power and Improved Asynchronous Circuit Techniques”, Oct., 1986, IEEE Journal of Solid-State Circuits, vol. SC-21. No. 5, pp. 692-703.
Manoj Franklin, et al., “Embedded RAM Testing”, IEEE, 1995, pp 29-33.
Andre Ivanov, Department of Electrical Engineering, University of British Columbia, “Design for Testability and Built-In Self-Test of Integrated Circuits and Systems: How These Can Add Value to Your Products”, 1996, pp. 712-717.
Kobayashi et al., “A 10-&mgr;W Standby Power 256K CMOS SRAM”, Oct. 1985, IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, pp. 935-939.
L. Lucas, et al., “Design Methodology of a Test Chip for a Portable 8ns 10 Ports Register File”, IEEE 1995 Custom Integrated Circuits Conference, 1995, pp. 29-32.
M. Nicolaidis, et al., “Trade-Offs in Scan Path and BIST Implementations for RAMs”, Journal of Electronic Testing: Theory and Applications, pp. 5, 273-283, 1994.
Junji Nishimura, Advantest Corporation, “New Testing Devices Are Responding to Higher Performance in Megabit Age”, Hi-Tech

Affiliated with

Also associated with

Rating

Scan path circuitry including a programmable delay circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scan path circuitry including a programmable delay circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scan path circuitry including a programmable delay circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2473120