Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-05-15
2009-11-17
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
07620865
ABSTRACT:
One may use a new technique to determine the placement of exclusive-ors in each scan string of a chip to achieve improved test vector compression, and one may combine this technique with methods to minimize the overhead of the exclusive-or logic, to eliminate clock enable logic for multiple scan strings, to minimize the changes to existing test logic insertion and scan string reordering, and to minimize the test vector compression computation time.
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Connolly Bove & Lodge & Hutz LLP
Kerveros James C
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