Scan test circuit

Details Scan test circuit Scan test circuit

2006-12-19

2006-12-19

Chung, Phung My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

07152195

ABSTRACT:
The scan test circuit according to one embodiment of the present invention includes a noninversion/inversion control circuit inserted and connected between a sequential circuit and a combinational circuit included in a path to be subjected to a scan test, the noninversion/inversion control circuit not inverting or inverting scan data output from the sequential circuit, on outside of said sequential circuit at arbitrary timing.

REFERENCES:
patent: 4856002 (1989-08-01), Sakashita et al.
patent: 5329532 (1994-07-01), Ikeda et al.
patent: 6134688 (2000-10-01), Sachdev
patent: 6189115 (2001-02-01), Whetsel
patent: 6189128 (2001-02-01), Asaka
patent: 6708303 (2004-03-01), Gallia
patent: 2004/0237015 (2004-11-01), Abdel-Hafez et al.
patent: 2002-289776 (2002-10-01), None

Affiliated with

Also associated with

Rating

Scan test circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scan test circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scan test circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3704322