Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-09-30
2002-11-19
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C714S741000, C714S742000, C703S013000, C703S015000
Reexamination Certificate
active
06484280
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention deals with the testing of complex digital integrated circuits using scan path of functional blocks.
2. Art Background
Complex integrated circuits such as system-on-a-chip (SOC) devices must be tested during manufacture. Improvements in process technology and in design tools allow denser, more complex, and faster SOC devices to be designed. Higher levels of integration and fewer external pins, compared to the amount of on-chip functionality, results in the reduced accessibility of internal functional elements for testing.
Device testing is performed using automated test equipment (ATE). Improving the controllability and observability of internal nodes of a device-under-test (DUT) increases the testability and achievable fault coverage for a DUT. In order to test a DUT with a reasonable confidence of weeding out nonfunctional parts, access to internal nodes within a device is needed.
Access to otherwise inaccessible internal nodes can be obtained by designing scan path capability into a device to be tested which can then be accessed through a test access port (TAP). Suitable scan path and TAP architectures known to the art include IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture.
Complex SOC devices are often designed and implemented as series of interconnected functional blocks, each of which can be tested independently. Each functional block can be surrounded by a test wrapper that consists of specific scan path cells. Scan path cells on selected input lines pass block input signals during normal operation, and pass shifted test signals during device test. Scan path cells on selected output lines latch specific block output signals. This arrangement allows for complex testing using a minimum of device pins. The input and output scan path cells are connected as long shift registers.
During test, (1) the operation of the device is stopped, (2) test vectors are clocked into input scan path cells, (3) the device clock toggled, and (4) the output scan path cells are clocked out and compared with a reference pattern to verify correct operation. This operation may be repeated thousands or millions of times. The potential fault coverage using this method may be quite high, but the amount of data that must be moved in and out of the device in serial fashion may result in significant test times.
Device testing is preferably performed at the actual operating speed of the DUT. The use of scan path capability does not allow continuous at-speed access to internal nodes of a device. Nevertheless, at-speed testing using scan path capability is known to the art by carefully controlling the device clock for one or more at-speed clock periods between the relatively long periods needed to load suitable test patterns.
Test patterns used for scan path testing are developed as is known to the art using one or more of the following schemes. First, actual device design data is used to generate block level structural test patterns, possibly reflecting expected defects and fault models. Next, behavioral models of the design in question may be used to develop functional test patterns. Finally, pseudo-random sequences may be used to automatically generate test patterns.
As with many other aspects of the semiconductor industry, time is money, and test time is expensive. What is needed is an improved approach to testing complex devices such as SOC devices.
SUMMARY OF THE INVENTION
An inexpensive system-on-a chip (SOC) device tester that makes use of SOC device design data, scan path, and reconfigurable logic. The SOC design is decomposed into functional blocks and surrounded by scan path cells. The high-level (Verilog or VHDL) simulation model of a chosen functional block, which is assumed to be correct, is loaded into a field programmable gate array (FPGA) or similar device. A test pattern is applied to the chosen functional block using the scan path cells, and is also applied to the FPGA simulation of the chosen block. After toggling the clock, the results are read out and compared. If the result vectors from the chosen functional block and its FPGA simulation fail to match, a record is created for further analysis. The FPGA may be rapidly reconfigured to test other blocks of the SOC device. The FPGA may also be used to provide appropriate signal levels on other pins of the SOC device.
REFERENCES:
patent: 4853622 (1989-08-01), Brust
patent: 5475624 (1995-12-01), West
patent: 5812561 (1998-09-01), Giles et al.
patent: 6041429 (2000-03-01), Koenemann
patent: 6286119 (2001-09-01), We et al.
Agilent Technologie,s Inc.
Martin Robert T.
Moise Emmanuel L.
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