Scan path circuitry for programming a variable clock pulse width

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

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G01R 3128

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061158364

ABSTRACT:
A circuit for generating a pulse including a scan register having a first scan bit; first logic device receiving a first signal and generating a second signal; and a programmable delay circuit coupled to the scan register and the first logic device. The programmable delay circuit receives the second signal and generates a delayed second signal after a programmable period of time. The programmable period of time is determined by the first scan bit. The circuit also includes a logic circuit that recevies the second signal and the delayed second signal. The logic circuiit outputs the pulse having a pulse width proportional to the programmable period of time.

REFERENCES:
patent: 3980901 (1976-09-01), Tokuda
patent: 4223396 (1980-09-01), Kinoshita
patent: 4272832 (1981-06-01), Ito
patent: 4286174 (1981-08-01), Dingwall
patent: 4355377 (1982-10-01), Sud et al.
patent: 4757214 (1988-07-01), Kobayashi
patent: 4767947 (1988-08-01), Shah
patent: 4797585 (1989-01-01), Segawa et al.
patent: 4843255 (1989-06-01), Stuebing
patent: 4894791 (1990-01-01), Jiang et al.
patent: 4951254 (1990-08-01), Ontrop et al.
patent: 4985643 (1991-01-01), Proebsting
patent: 4995039 (1991-02-01), Sakashita et al.
patent: 5003513 (1991-03-01), Porter et al.
patent: 5039875 (1991-08-01), Chang
patent: 5072132 (1991-12-01), Samaras et al.
patent: 5130568 (1992-07-01), Miller et al.
patent: 5151614 (1992-09-01), Yamazaki et al.
patent: 5161160 (1992-11-01), Yaguchi et al.
patent: 5163168 (1992-11-01), Hirano et al.
patent: 5172012 (1992-12-01), Ueda
patent: 5177375 (1993-01-01), Ogawa et al.
patent: 5185745 (1993-02-01), Manca, Jr.
patent: 5218237 (1993-06-01), Mao
patent: 5231314 (1993-07-01), Andrews
patent: 5272390 (1993-12-01), Watson, Jr. et al.
patent: 5306958 (1994-04-01), Reddy et al.
patent: 5321317 (1994-06-01), Pascucci et al.
patent: 5325367 (1994-06-01), Dekker et al.
patent: 5343082 (1994-08-01), Han et al.
patent: 5343085 (1994-08-01), Fujimore et al.
patent: 5384737 (1995-01-01), Childs et al.
patent: 5396110 (1995-03-01), Houston
patent: 5406566 (1995-04-01), Obara
patent: 5420467 (1995-05-01), Huott et al.
patent: 5428311 (1995-06-01), McClure
patent: 5438550 (1995-08-01), Kim
patent: 5476053 (1995-12-01), Wuidart et al.
patent: 5590089 (1996-12-01), Roohparvar
patent: 5654988 (1997-08-01), Heyward et al.
patent: 5663921 (1997-09-01), Pascucci et al.
patent: 5815510 (1998-09-01), Jones et al.
Micron Semiconductor, Inc., MT58LC64K18B2.times.18 Synchronous SRAM, Revised Apr. 9, 1996, pp. 1-12.
Paradigm, PDM44018, 64K.times.18 Fast CMOS Synchronous Static SRAM with Burst Counter, pp. 6-21-6-29.
Hitachi Semiconductor, HM67B1864 Series (Target Spec.) 64K.times.18 Bits Synchronous Fast Static RAM with Counter and Self-Timed Write, Mar. 31, 1994, Prod. Preview, 10 pages total.
Motorola Semiconductor Technical Data, Product Review MCM67B618 64K.times.18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self-Timed Write, Rev. 3 Jan. 1993, pp. 1-9.
Cypress Semiconductor, Preliminary CU7C1031 CY7C1032 64K.times.18 Synchronous Cache RAM, Jan. 1993--Revised May 1993, pp. 1-13.
Stan Runyon, "EDA Software Syntest Stresses Speed Fault simultator blasts million-gate designs".
David DiMarco, et al., "FA 9.8: A 200MHz 256kB Second-Level Cache with 1.6GB/s Data Bandwidth" 1996 IEEE International Solid-State Circuits Conference, ISSCC96/Session9/SRAM/Paper FA 9.8, Feb. 9, 1996.
Manuel J. Raposa, Dual Port Static Ram Testing, Paper 20.3, 1988 International Test Conference, pp. 362-368.
Junji Nishimura, Advantest Corporation, "New Testing Devices Are Responding to Higher Performance in Megabit Age", Hi-Tech Report: Memroy Testing Technology, Jan. 1989, pp. 96-101.
Andre Ivanov, Department of Electrical Engineering, University of British Columbia, "Design for Testability and Built-In-Self-Test of Integrated Circuits and Systems: How These Can Add Value to Your Products", 1996, pp. 712-717.
M. Nicolaidis, et al., "Trade-offs in Scan Path and BIST Implementations for RAMs", Journal of Electronic Testing: Theory and Applications, pp. 5, 273-283, 1994.
Ad J. Van De Goor, et al., "Effective March Alogorithms for Testing Single-Order Addressed Memories", Journal of Electronics Testing: Theory and Applications, 5, 337-345, 1994.
D. Roy Chowdhury, et al., "Cellular automata based pattern generator for testing RAM", IEE Proceedings -E. vol. 139. No. 6. Nov. 1992, pp. 469-476.
Kewal K. Saluja, et al., "Test Pattern Generation for API Faults in RAM", IEEE Transactions on Computers, vol. C-34, No. 3, Mar. 1985, pp. 284-287.
G. M. Ettinger, et al., "Memory-based logic sequence generation", Microprocessors and Microsystems, vol. 9, No. 9, Nov. 1985, pp. 446-451.
L. Lucas, et al., "Design Methodology of a Test Chip for a Portable 8ns 10 Ports Register File", IEEE 1995 Custom Integrated Circuits Conference, 1995, pp. 29-32.
Manoj Franklin, et al., "Embedded RAM Testing", IEEE, 1995, pp. 29-33.
Zuxi Sun, "Self-Testing of Embedded RAMs", 1984 International Test Conference, Paper 4.3, pp. 148-156.
Wendell et al., "A 3.5ns, 2Kx9 Self Timed SRAM", 1990 IEEE, 1990 Symposium on VLSI Circuits, pp. 49-50.
Bonges,III et al., "A 576K 3.5-ns Access BiCMOS ECL Static RAM with Array Built-in Self Test", 1992 IEEE, pp. 649-656.
Chappell et al., A 2-ns Cycle, 3.8-ns Access 512kb CMOS ECL SRAM with a Fully Pipellined Architecture, Nov. 1991, IEEE Journal of Solid-State Circuits, vol. 26, No. 11, pp. 1577-1585.
Childs et al., "An 18-ns 4Kx4 CMOS SRAM", Oct. 1984, IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 545-551.
Flannagan et al., "Two 13-ns 64K CMOS SRAM's with Very Low Active Power and Improved Asynchronous Circuit Techniques", Oct. 1986, IEEE Journal of Solid-State Circuits, vol. SC-21. No. 5, pp. 692-703.
Kobayashi et al., "A 10-.mu.W Standby Power 256K CMOS SRAM", Oct. 1985, IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, pp. 935-939.
Williams et al., An Experimental 1-Mbit CMOS SRAM with Configurable Organization and Operation, Oct. 1988, IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1085-1093.

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