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Selected: P

Phase shift adjusting method and circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error detection for synchronization control
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Phase shifter with reduced linear dependency

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Phase shifter with reduced linear dependency

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Phase-detector-less method and apparatus for minimizing skew...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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PHS terminal device and method of receiving PHS data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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PHS terminal device and method of receiving PHS data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Physical block address recovery apparatus system and method...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Physical coding sublayer for a multi-pair gigabit transceiver

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Physical coding sublayer for a multi-pair gigabit transceiver

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Physical packaging position information processing system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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PICA system timing measurement and calibration

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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Piggybacking of ECC corrections behind loads

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Pin coupler for an integrated circuit tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pipeline architecture for maximum a posteriori (MAP) decoders

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Pipeline architecture for maximum a posteriori (MAP) decoders

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Pipeline circuit with a test circuit with small circuit scale an

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Pipeline of additional storage elements to shift...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pipelined add-compare-select circuits and methods, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Pipelined architecture implementing recursion processes for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Pipelined architecture to decode parallel and serial...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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