Pipeline architecture for maximum a posteriori (MAP) decoders

Details Pipeline architecture for maximum a posteriori (MAP) decoders Pipeline architecture for maximum a posteriori (MAP) decoders

2011-03-15

2011-03-15

Abraham, Esaw T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S794000, C714S795000, C375S262000, C375S341000

Reexamination Certificate

active

07908545

ABSTRACT:
The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture as developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

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