Pipelined add-compare-select circuits and methods, and...

Details Pipelined add-compare-select circuits and methods, and... Pipelined add-compare-select circuits and methods, and...

2006-03-28

2006-03-28

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07020831

ABSTRACT:
Digital communications devices having high-speed add-compare-select circuits, and methods for designing the same. The add-compare-select circuits include logic segments separated by delay devices. The separation of the logic segments allows for pipelining of the add-compare-select processes and advantageous circuit retiming. The pipelining and advantageous circuit retiming permit the digital communications devices to be clocked at higher rates than similar digital communications devices having conventional add-compare-select circuits.

REFERENCES:
patent: 4606027 (1986-08-01), Otani
patent: 5418795 (1995-05-01), Itakura et al.
patent: 6111835 (2000-08-01), Honma
patent: 6148431 (2000-11-01), Lee et al.
patent: 6212664 (2001-04-01), Feygin et al.

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