Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2000-04-24
2004-11-23
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C714S746000, C375S219000, C375S341000, C375S348000
Reexamination Certificate
active
06823483
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to Physical Coding Sublayers in a high-speed multi-pair communication system. More particularly, the invention relates to a Physical Coding Sublayer that operates in accordance with the IEEE 802.3ab standard for Gigabit Ethernet (also called 1000 BASE-T standard).
2. Description of Related Art
In recent years, local area network (LAN) applications have become more and more prevalent as a means for providing local interconnect between personal computer systems, work stations and servers. Because of the breadth of its installed base, the 10 BASE-T implementation of Ethernet remains the most pervasive if not the dominant, network technology for LANs. However, as the need to exchange information becomes more and more imperative, and as the scope and size of the information being exchanged increases, higher and higher speeds (greater bandwidth) are required from network interconnect technologies. Among the high-speed LAN technologies currently available, fast Ethernet, commonly termed 100 BASE-T, has emerged as the clear technological choice. Fast Ethernet technology provides a smooth, non-disruptive evolution from the 10 megabit per second (Mbps) performance of 10 BASE-T applications to the 100 Mbps performance of 100 BASE-T. The growing use of 100 BASE-T interconnections between servers and desktops is creating a definite need for an even higher speed network technology at the backbone and server level.
One of the more suitable solutions to this need has been proposed in the IEEE 802.3ab standard for gigabit Ethernet, also termed 1000 BASE-T. Gigabit Ethernet is defined as able to provide 1 gigabit per second (Gbps) bandwidth in combination with the simplicity of an Ethernet architecture, at a lower cost than other technologies of comparable speed. Moreover, gigabit Ethernet offers a smooth, seamless upgrade path for present 10 BASE-T or 100 BASE-T Ethernet installations.
In order to obtain the requisite gigabit performance levels, gigabit Ethernet transceivers are interconnected with a multi-pair transmission channel architecture. In particular, transceivers are interconnected using four separate pairs of twisted Category-5 copper wires. Gigabit communication, in practice, involves the simultaneous, parallel transmission of information signals, with each signal conveying information at a rate of 250 megabits per second (Mb/s). Simultaneous, parallel transmission of four information signals over four twisted wire pairs poses substantial challenges to bidirectional communication transceivers, even though the data rate on any one wire pair is “only” 250 Mbps.
In particular, the Gigabit Ethernet standard requires that digital information being processed for transmission be symbolically represented in accordance with a five-level pulse amplitude modulation scheme (PAM-5) and encoded in accordance with an 8-state Trellis coding methodology. Coded information is then communicated over a multi-dimensional parallel transmission channel to a designated receiver, where the original information must be extracted (demodulated) from a multi-level signal. In Gigabit Ethernet, it is important to note that it is the concatenation of signal samples received simultaneously on all four twisted pair lines of the channel that defines a symbol. Thus, demodulator/decoder architectures must be implemented with a degree of computational complexity that allows them to accommodate not only the “state width” of Trellis coded signals, but also the “dimensional depth” represented by the transmission channel.
Computational complexity is not the only challenge presented to modern gigabit capable communication devices. Perhaps, a greater challenge is that the complex computations required to process “deep” and “wide” signal representations must be performed in an extremely short period of time. For example, in gigabit applications, each of the four-dimensional signal samples, formed by the four signals received simultaneously over the four twisted wire pairs, must be efficiently decoded within a particular allocated symbol time window of about 8 nanoseconds.
The trellis code constrains the sequences of symbols that can be generated, so that valid sequences are only those that correspond to a possible path in the trellis diagram of FIG.
5
. The code only constrains the sequence of 4-dimensional code-subsets that can be transmitted, but not the specific symbols from the code-subsets that are actually transmitted. The IEEE 802.3ab Draft Standard specifies the exact encoding rules for all possible combinations of transmitted bits.
One important observation is that this trellis code does not tolerate pair swaps. If, in a certain sequence of symbols generated by a transmitter operating according to the specifications of the 1000 BASE-T standard, two or more wire pairs are interchanged in the connection between transmitter and receiver (this would occur if the order of the pairs is not properly maintained in the connection), the sequence of symbols received by the decoder will not, in general, be a valid sequence for this code. In this case, it will not be possible to properly decode the sequence. Thus, compensation for a pair swap is a necessity in a gigabit Ethernet transceiver.
SUMMARY OF THE INVENTION
In an apparatus embodiment of the invention, a physical coding sublayer (PCS) receiver core circuit decodes a plurality of symbols based on encoding parameters. The symbols are transmitted using the encoding parameters according to a transmission standard. The received symbols are skewed within a symbol clock time by respective skew intervals. A PCS receiver encoder generator generates the encoding parameters. In a method embodiment of the invention, a plurality of symbols are decoded based on encoding parameters. The symbols are transmitted using the encoding parameters according to a transmission standard. The received symbols are skewed within a symbol clock time by respective skew intervals and encoding parameters are generated.
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Fineberg et al. “Analysis of 100 Mb/s Ethernet for the Whitney commodity computing testbed; IEEE, Seventh Symposium on th Frontiers of Massively Parallel Computation, pp. 276-283, Feb. 21-25, 1999”.*
Huimin Xia et al. “A mixed-signal behavioral level implementation of 1000BASE-X physical layer for gigabit Ethernet; IEEE International Symposium on Circuits and Systems, pp. 431-434 vol. 1, Jul. 1999”.*
Crouch et al. “Coding in 100VG-AnyLAN, Hewlett-Packard Journal, pp. 27-32, vol. 4; Aug. 1995.”*
Simon E. C. Crouch, et al., “Coding in 100VG-AnyLAN,”Hewlett-Packard Journal, Aug. 1995, pp. 27-32, vol. 46, No. 4, Palo Alto, California. (XP 000525583).
IEEE Std 802.3ab-1999 (Supplement to IEEE Std 802.3, 1998 Edition), entitled Supplement to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications—Physical Layer Parameters and Specifications for 1000 Mb/s Operation Over 4-Pair of Category 5 Balanced Copper Cabling, Type 1000BASE-T.
Broadcom Corporation
Lamarre Guy J.
McAndrews Held & Malloy Ltd.
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