Pipelined architecture implementing recursion processes for...

Details Pipelined architecture implementing recursion processes for... Pipelined architecture implementing recursion processes for...

2007-09-04

2007-09-04

Lamarre, Guy (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S796000, C714S774000, C714S786000

Reexamination Certificate

active

10769662

ABSTRACT:
A method and apparatus for performing a recursion process on a data block for error correction. The disclosure describes concurrently operating pipelined sub-processes that decode the data block with error correction. The pipelined sub-processes are implemented as sub-circuits of an integrated circuit. The output data from each sub-process is stored for input by a subsequent sub-process of the pipelined sub-processes.

REFERENCES:
patent: 6304996 (2001-10-01), Van Stralen et al.
patent: 6718504 (2004-04-01), Coombs et al.
patent: 2003/0097633 (2003-05-01), Nguyen

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