Piggybacking of ECC corrections behind loads

Details Piggybacking of ECC corrections behind loads Piggybacking of ECC corrections behind loads

2006-05-09

2006-05-09

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S703000, C714S052000

Reexamination Certificate

active

07043679

ABSTRACT:
An apparatus including circuitry configured to detect and correct an ECC error in a non-targeted portion of a load access to a first data in a memory. An ECC error check circuit is configured to convey a first indication in response to detecting an error in a non-targeted first portion of the first data. A microcode unit is coupled to receive the first indication that the ECC check circuit has detected the ECC error and in response to the indication dispatch a first microcode routine stored by the microcode unit. The first microcode routine includes instructions which, when executed, correct the ECC error in the first portion. Correction of the error in the first portion does not include cancellation of data corresponding to the load access.

REFERENCES:
patent: 5659678 (1997-08-01), Aichelmann et al.
patent: 5689727 (1997-11-01), Bonke et al.
patent: 5991911 (1999-11-01), Zook
patent: 6092182 (2000-07-01), Mahalingaiah
patent: 6101614 (2000-08-01), Gonzales et al.
patent: 6161208 (2000-12-01), Dutton et al.
patent: 6175941 (2001-01-01), Poeppelman et al.

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