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Processor to JTAG test access port interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Processor with packet data flushing feature

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Product code based forward error correction system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Product code based forward error correction system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Product code iterative decoding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Product code with interleaving to enhance error detection...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Production interface for an integrated circuit test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Program analyzing apparatus which categorizes variables into dom

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Program debugging support device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Program for error correcting process included in error...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Program patching of a ROM

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Program verify method for OTP memories

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Program, test apparatus and testing method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Program-controlled unit and method for identifying and/or...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Programmable address space built-in self test (BIST) device...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Programmable array built-in self test method and controller...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Programmable array built-in self test method and system for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Programmable built in self test for embedded DRAM

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Programmable built in self test of memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Programmable built-in self-test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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