Processor with packet data flushing feature

Details Processor with packet data flushing feature Processor with packet data flushing feature

2005-07-05

2005-07-05

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S774000

Reexamination Certificate

active

06915480

ABSTRACT:
A network processor or other type of processor includes first classification circuitry, scheduling circuitry and second classification circuitry. The first classification circuitry is configured to determine for a given packet received by the processor whether the packet has one or more errors. The scheduling circuitry in an illustrative embodiment receives an indication of the error determination made by the first classification circuitry, and based on the indication controls the dropping of the given packet from the processor memories if the packet has one or more errors, e.g., via a flush transmit command. The second classification circuitry, which may be implemented as a single classification engine or a set of such engines, may be configured to perform at least one classification operation for the given packet, e.g., if the packet is supplied thereto by the scheduling circuitry.

REFERENCES:
patent: 5720032 (1998-02-01), Picazo et al.
patent: 6115394 (2000-09-01), Balachandran et al.
patent: 6754200 (2004-06-01), Nishimura et al.

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