Programmable built-in self-test architecture

Details Programmable built-in self-test architecture Programmable built-in self-test architecture

2009-07-13

2011-11-29

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S733000

Reexamination Certificate

active

08069385

ABSTRACT:
A PBIST architecture is described. A data path circuit is configured for bit-to-associated bit comparisons of expected result data read from a tile with the expected result data read from result memory. The data path circuit is configured to write a first type of failure indication to first failure memory responsive to a data 0 being read from the result memory and a data 1 being read from the tile for a bit-to-associated bit comparison failure. The data path circuit is further configured to write a second type of failure indication to second failure memory responsive to a data 1 being read from the result memory and a data 0 being read from the tile for the bit-to-associated bit comparison.

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