Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-05-17
2011-05-17
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S030000
Reexamination Certificate
active
07945823
ABSTRACT:
A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator (202) that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (216). An address range selector circuit (230) can limit the range of addresses generated by an address generator (234). Once defective addresses for a first range have been detected, an address range selector circuit (230) can test another range. An entire address range can thus be tested regardless of the depth of a fault address store (216).
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Doddamane Ramesha
Krishnan Gopalakrishnan Perur
Singh Tarjinder
Vadlamani Eswar
Haverstock & Owens LLP
NetLogic Microsystems, Inc.
Ton David
LandOfFree
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