Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1995-01-04
2001-05-22
Wright, Norman Michael (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000, C714S734000, C714S742000
Reexamination Certificate
active
06237120
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electronics apparatus such as exclusive-use micro-controllers and, more particularly to an electronics apparatus in which a central processing unit (CPU) provided as an address controller or the like and a read-only memory (ROM) in which programs and data are stored in a fixed condition are integrated as one chip.
2. Description of the Related Art
Conventional electronics apparatus such as a video cassette recorder (VCR) having a built-in camera, for example, have mounted thereon a custom LSI (large scale integration) integrated electronics apparatus on one chip as control means, i.e., a so-called micro-controller for controlling the entirety or part of the electronics apparatus.
The micro-controller is an exclusive-use microcomputer which is composed of a central processing unit (CPU), a memory such as a read-only memory (ROM) and a random access memory (RAM) and a peripheral circuit such as an input/output (I/O) port or the like.
The CPU acts as an address controller to control the access to the memories or the like or acts as a processor to execute a program. Information such as programs, data and so on for controlling the mounted electronics device are stored in the ROM in the form of firmware. The RAM provides the CPU with a working area or the like to execute a program and the peripheral circuit is used to communicate with the external circuits. Accordingly, mass-production is indispensable for providing inexpensive custom LSI electronics apparatus such as micro-controllers or the like.
The firmware capacity stored in the ROM of the micro-controller is increased yearly as the performance of the electronics apparatus is enhanced and refined. Considering a VCR having a built-in camera, for example, the above-mentioned capacity is expected to exceed the present capacity of several 10s of kilobytes and to exceed 100k bytes after a few years.
The largest efforts are made to improve on the quality of the firmware by structured programming and various inspections so as to prevent bugs from taking place in the firmware after the micro-controller is mass-produced. Even when a bug is discovered after the micro-controller is mass-produced, a lot of money, plenty of time and people are needed to cope with the bugs by some suitable means such as correcting the firmware by the addition of an external circuit or the like and by mass-producing and exchanging a micro-controller in which a bug patch is carried out. However, in the case of electronics apparatus such as the built-in camera type VCR which uses assembly parts of high accuracy, a bug patch by the addition of an external circuit becomes substantially impossible.
OBJECTS AND SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide an improved electronics apparatus in which the aforementioned shortcomings and disadvantages encountered with the prior art can be eliminated.
More specifically, it is an object of the present invention to provide an electronics apparatus in which even when a bug in the firmware is discovered after the electronics apparatus is mass-produced or even when the firmware must be modified, such problems can be solved readily and easily by supplying in one step a correcting information thereto from the outside.
Another object of the present invention is to provide an electronics apparatus in which a countermeasure requiring much money, time and people such as the addition of external circuits, another mass-production of electronics apparatus or the like can be made unnecessary.
A further object of the present invention is to provide an electronics apparatus which can be prevented from being lowered in reliability by the addition of an external circuit or the like.
As an aspect of the present invention, an electronics apparatus integrated on a single substrate and in which a read-only information storage means for storing firmware, address control means for performing address control, and input means for inputting information supplied thereto from an external source comprise correcting information storage means for receiving correcting information input thereto from the external source through the input means and storing the correcting information, wherein the correcting information is indicative of a modification for a defective information part stored in the read-only information storage means, and switching means for selectively switching the access by the address control means from the defective information part in the read-only information storage means to the correcting information in the correcting information storage means.
REFERENCES:
patent: 4028678 (1977-06-01), Moran
patent: 4028679 (1977-06-01), Divine
patent: 4028683 (1977-06-01), Divine et al.
patent: 4028684 (1977-06-01), Divine et al.
patent: 4051460 (1977-09-01), Yamada et al.
patent: 4095278 (1978-06-01), Kihara
patent: 4150428 (1979-04-01), Inrig et al.
patent: 4218757 (1980-08-01), Drogichen
patent: 4291375 (1981-09-01), Wolf
patent: 4296470 (1981-10-01), Fairchild et al.
patent: 4319343 (1982-03-01), Powell
patent: 4400798 (1983-08-01), Francis et al.
patent: 4424574 (1984-01-01), Enoki et al.
patent: 4456966 (1984-06-01), Bringol et al.
patent: 4490783 (1984-12-01), McDonough et al.
patent: 4490812 (1984-12-01), Guterman
patent: 4517643 (1985-05-01), Bannai
patent: 4542453 (1985-09-01), Patrick et al.
patent: 4610000 (1986-09-01), Lee
patent: 4620273 (1986-10-01), Mitani et al.
patent: 4709324 (1987-11-01), Kloker
patent: 4727476 (1988-02-01), Rouchon
patent: 4745572 (1988-05-01), Wilburn
patent: 4751677 (1988-06-01), Hirayama et al.
patent: 4751703 (1988-06-01), Picon et al.
patent: 4769767 (1988-09-01), Hilbrink
patent: 4802119 (1989-01-01), Heene et al.
patent: 4819154 (1989-04-01), Stiffler et al.
patent: 4831517 (1989-05-01), Crouse et al.
patent: 4905200 (1990-02-01), Pidsosny et al.
patent: 4942541 (1990-07-01), Hoel et al.
patent: 4972481 (1990-11-01), Santesson
patent: 5051897 (1991-09-01), Yamaguchi et al.
patent: 5063499 (1991-11-01), Garber
patent: 5077737 (1991-12-01), Leger
patent: 5199032 (1993-03-01), Sparks et al.
patent: 5214771 (1993-05-01), Clara et al.
patent: 5289416 (1994-02-01), Iwai
patent: 5305460 (1994-04-01), Kaneko et al.
patent: 5357627 (1994-10-01), Miyazawa
patent: 5408672 (1995-04-01), Miyazawa et al.
patent: 5454100 (1995-09-01), Sagane
patent: 0 263 447 A2 (1988-04-01), None
patent: 0 428 005 A2 (1991-05-01), None
patent: 0 458 559 A2 (1991-11-01), None
patent: 8101113499 (1981-07-01), None
patent: 007067 (1983-03-01), None
patent: 62-249231 (1987-10-01), None
patent: 1-065633 (1989-03-01), None
patent: 1-099129 (1989-04-01), None
patent: 1-114941 (1989-05-01), None
Rosenberg, J.M.; Dictionary of Computers, Information Processing & Telecommunications, 2 ed. pp. 94, 239, 292, 301, 327, 382, 394, and 613, 1984.*
D. P. Siewiorek et al., Computer Structures: Principles and Examples, 1982, McGraw-Hill, pp. 581, and 612-614.*
Computer Structures: Principles and Examples, McGraw-Hill Publishing Company, copyright 1982,, Daniel P. Siewiorek et al., pp. 581, 612-614.
U.S. application No. 08/110,818, Yamamoto et al., filed Aug. 23, 1993.
U.S. application No. 08/001,311, Shimada et al., filed Jan. 6, 1993.
U.S. application No. 08/004,932, Yamamoto et al., filed Jan. 15, 1993.
U.S. application No. 08/122,904, Yamamoto et al., filed, Sep. 16, 1992
Short and Long ROS Patch, H. Trinh IBM Technical Disclosure Bulletin—vol. 24, No. 3—Aug. 1981 pp 1379-1382.
Charlie Meleaur: “Applications for Microcomputers with E2PROM” Electro/ 86 and Mini/Micro Northeast 11(1986), Conference Record, Los Angeles, CA, USA, pp. 1-9.
IBM Technical Disclosure Bulletin, vol. 26 No. 10B, Mar. 1984, New York, USA, pp. 2-3, L. Weiss: “Path Microcode Change Level Check”.
IBM Technical Disclosure Bulletin, vol. 30, No. 5, Oct. 1987, “On-Site ROS Patch Mechanism” pp. 4-5.
IBM Technical Disclosure Bulletin, vol. 31, No. 1, Jun. 1988, “Dual Indirect RAM/ROM Jump Tables for Firmware Updates” pp. 294-289.
Patent Abstracts
Furui Sunao
Matsuno Katsumi
Shimada Keiichiro
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Sony Corporation
Wright Norman Michael
LandOfFree
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