Processor to JTAG test access port interface

Details Processor to JTAG test access port interface Processor to JTAG test access port interface

2011-03-15

2011-03-15

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

07908533

ABSTRACT:
Method and apparatus for operating for operating an Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1 compliant Joint Test Action Group (JTAG) Test Access Port (TAP) controller are disclosed. An example apparatus includes write logic that is configured to operationally interface with a TAP controller and a processor. The write logic is further configured to receive, from the processor, data for initializing the apparatus and operating the TAP controller, convert at least a portion of the data from a parallel format to a serial format and communicate the converted data to the TAP controller.

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Test Technology Standards, Committee Of The IEEE Comuters., “IEEE Standard Test Access Port and”, IEEE Std 1149.-1990, Document provided by IHS Licensee=Global Electronic Production/1111125001, User=CINDYP, Oct. 24, 2003, 12:50:37 MDT, (Jun. 17, 1993), 139 pgs.
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