Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-05-17
2003-11-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S230030
Reexamination Certificate
active
06651203
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor memories and more particularly, to an apparatus for testing memory devices using an on chip data pattern generator.
2. Description of the Related Art
The rapid growth in circuit complexity has increased the difficulty and cost of testing memories. Development of high density memories introduces a new dimension in testing complexity. For example, higher speed synchronous DRAMs need includes more complex and more time consuming pattern testing. Using test systems for memory testing may require additional equipment to maintain current levels of throughput. It is typically expensive to add additional testers at to maintain the throughput needed for more complex high-speed memory devices.
Another issue concerning the testing of both the current and future generations of high density memories involves chip frequencies relative to the speed and accuracy of the testers. It is becoming more difficult to find high-speed test systems that can keep up with the chips being tested. Typically, device frequency has been growing faster than the accuracy of testers. At the same time, the test equipment is getting more complex. The pin counts are getting higher and therefore the accuracy needs to be managed over more pins. Further, maintaining costs at a reasonable level and performing the tests in a reasonable time frame are also an issue for manufactures and testers.
In semiconductor memory testing, a chip is tested by writing a known data pattern to memory cells in the array by an external testing device. The data pattern is then read back to the device and compared to the known data pattern. Data patterns may include a physical pattern, a logical pattern and/or a checker pattern, for example. Referring to
FIGS. 1A-1C
, for semiconductor memory devices, such as dynamic random access memories (DRAMs), bitlines BL and complementary bitlines {overscore (BL)} (hereinafter BL bar) paired and coupled to a sense amplifier SA. To activate (read from or write to) a memory cell (denoted by circles), a sense amplifier SA and a wordline WL need to be selected. BL and BL bar each have memory cells associated therewith. For example, in
FIG. 1A
, a physical “1” data pattern is stored as a 1 on memory cells associated with BLs and as a zero on memory cells associated with BL bars. This means all memory cells have charged capacitors. For
FIG. 1B
, the data pattern is that for a logical “1”. In this case, all is are stored in the array which means that half of the memory cells have charged capacitors and half do not. In
FIG. 1C
, a checkerboard pattern is implemented having alternating is and Os and alternating charged and discharged memory cell capacitors.
As illustrated in
FIGS. 1A-1C
, physical data corresponds to the content or meaning or the storage capacitor. In the case of a physical 1, the capacitor is charged and for a physical 0, the capacitor is discharged. For logical data, only the value at an input/output pin (DQ) is important. The term logical 1 (0) means if the memory cell is connected to BL or BL bar, a 1 (0) is read/written from/to the I/O-pin. A checkerboard pattern is also a physical data pattern having alternating charged or discharged capacitors. Logical patterns are more easily implemented since the address of the memory cells is not as important as for physical data patterns. For physical data patterns, BL or BL bar connection information is needed to provide appropriate testing. Therefore, address information is needed to correlate BL/BL bar to each memory cell and the data pattern. Due to the address information and the density of memory cells difficulties arise with respect to testing. This is due in part to the number of memory cells and the need to keep track of not only the data pattern addressed to each memory cell but also the locations of failed memory cells.
Chip manufacturing processes are not error free. Therefore each memory chip has to be carefully tested, typically using the data patterns described above. Testing costs are presently a major contributor to overall manufacturing costs of memory chips. The test costs may be reduced either by reducing the time required to test a chip and/or to increase the number of chips tested in parallel. The number of chips tested in parallel is usually limited by the number of input/output (I/O) channels a memory tester can handle. One way to increase the number of chips tested in parallel is to reduce the number of connections between the external tester and the chip under test. Assuming a tester can handle 1024 I/O channels and 130 channels are needed to test one chip, then 7 chips can be tested in parallel.
Therefore, a need exists for an apparatus for testing memory cells to both reduce costs of testing and reduce test time. A further need exists for an apparatus which reduces the number of channels needed to test each chip.
SUMMARY OF THE INVENTION
A semiconductor memory chip in accordance with the present invention includes a first memory array to be tested including a plurality of memory cells arranged in rows and columns, the memory cells being accessed to read and write data thereto by employing bitlines and wordlines, the data provided on input/output pins, and a pattern generator formed on the memory chip. The pattern generator further includes a programmable memory array including a plurality of memory banks, the memory banks having memory cells arranged in rows and columns, each bank being capable of storing data for a pattern to be generated for each of the input/output pins of the first memory array. A means for addressing the data stored in the programmable memory array to address individual data to be transmitted to and from the first memory array is included.
Another semiconductor memory chip includes a first memory array to be tested including a plurality of memory cells arranged in rows and columns, the memory cells being accessed to read and write data thereto by employing bitlines and wordlines, the data provided on input/output pins. A pattern generator is formed on the memory chip. The pattern generator further includes a programmable memory array including a plurality of memory banks, the memory banks having memory cells arranged in rows and columns, each bank being capable of storing data for a pattern to be generated for each of the input/output pins of the first memory array. A means for addressing the data stored in the programmable memory array to address individual data to be transmitted to and from the first memory array is also included. A pattern decoder for selecting a pattern from a plurality of patterns, stored in the memory banks, in accordance with an input signal. Outputs are coupled to the input/output pins of the first memory array to provide the individual data to be transmitted to and from the first memory array.
A DRAM memory chip in accordance with the invention includes a first memory array to be tested including a plurality of memory cells arranged in rows and columns, the memory cells being accessed to read and write data thereto by employing bitlines and wordlines. The data is provided on input/output pins. A pattern generator is formed on the memory chip. The pattern generator further includes a programmable memory array including a plurality of memory banks, the memory banks having memory cells arranged in rows and columns, each bank being capable of storing data for a pattern to be generated for each of the input/output pins of the first memory array. An input means for inputting the pattern data from a source external to the memory chip to the memory banks of the programmable memory is included. The pattern data is provided to the programmable memory prior to testing the memory chip. A means for addressing the data stored in the programmable memory array is included to address individual data to be transmitted to and from the first memory array. A pattern decoder selects a pattern from a plurality of patterns, stored in the memory banks, in accordance with an input signal. Outputs of the pattern generator are
De'cady Albert
Jackson Walker L.L.P.
Lamarre Guy
LandOfFree
On chip programmable data pattern generator for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with On chip programmable data pattern generator for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On chip programmable data pattern generator for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3170035