Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-10-13
2009-12-29
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000, C714S744000
Reexamination Certificate
active
07640471
ABSTRACT:
In a method and system for testing, a tester (110) is operable to communicate test signals (124, 126) at a tester clock speed, and a device (190) to be tested is operable to communicate the test signals (124, 126) at a device clock speed, the device clock speed being greater than the tester clock speed. A test module (120) is interposed between the tester (110) and the device (190) to enable data transfer between the tester (110) and the device (190) at their respective clock speeds. The test module (120) includes a memory module (250) capable of storing N samples of the test signals (124, 126) at a selectable one of the tester clock speed and the device clock speed. The memory module (250) is operable to provide the N samples at a selectable one of the tester clock speed and the device clock speed.
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Miao Yu
Smith Shawn C.
Vigrass Elizabeth
Brady III Wade J.
Tabone, Jr. John J
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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