Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-05-03
2008-11-04
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07447965
ABSTRACT:
Communications equipment can be tested using a test pattern encapsulated within a frame, and offsetting the test pattern in each successive frame. In equipment having a number of data latches receiving serial input, the introduction of the offset allows each latch, over time, to be exposed to the same pattern as the other latches. That is, the latches “see” different portions of the pattern at a given time, but over time, each can be exposed to the full pattern. Otherwise, each latch would “see” its own static pattern, different from the other latches, but the same over time with respect to itself. The offset can enhance diagnostic capabilities of the test pattern.
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Brink Robert D.
Hofmann, Jr. James Walter
Olsen Max J.
Schiessler Gary E.
Smith Lane A.
Agere Systems Inc.
Louis-Jacques Jacques
Merant Guerrier
Ryan & Mason & Lewis, LLP
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