Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-05-17
2002-03-12
DeCady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06357027
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor memory testing and more particularly, to an apparatus for testing memory devices using an on chip data comparison between input and output data patterns.
2. Description of the Related Art
The rapid growth in circuit complexity has increased the difficulty and cost of testing memories. Development of high density memories introduces a new dimension in testing complexity. For example, higher speed synchronous DRAMs need includes more complex and more time consuming pattern testing. Using test systems for memory testing may require additional equipment to maintain current levels of throughput. It is typically expensive to add additional testers at to maintain the throughput needed for more complex high-speed memory devices.
Another issue concerning the testing of both the current and future generations of high density memories involves chip frequencies relative to the speed and accuracy of the testers. It is becoming more difficult to find high-speed test systems that can keep up with the chips being tested. Typically, device frequency has been growing faster than the accuracy of testers. At the same time, the test equipment is getting more complex. The pin counts are getting higher and therefore the accuracy needs to be managed over more pins. Further, maintaining costs at a reasonable level and performing the tests in a reasonable time frame are also an issue for manufactures and testers.
In semiconductor memory testing, a chip is tested by writing a known data pattern to memory cells in the array by an external testing device. The data pattern is then read back to the device and compared to the known data pattern.
Chip manufacturing processes are not error free. Therefore each memory chip has to be carefully tested, typically using the data patterns described above. Testing costs are presently a major contributor to overall manufacturing costs of memory chips. The test costs may be reduced either by reducing the time required to test a chip and/or to increase the number of chips tested in parallel. The number of chips tested in parallel is usually limited by the number of input/output (I/O) channels a memory tester can handle. One way to increase the number of chips tested in parallel is to reduce the number of connections between the external tester and the chip under test. Assuming a tester can handle 1024 I/O channels and 130 channels are needed to test one chip, then 7 chips can be tested in parallel.
Referring to
FIG. 1
, a conventional test setup for testing memory chip is shown. A chip package
10
including a memory chip(s)
14
or a wafer
12
including a plurality of chips
14
may be tested using an external memory tester
16
. Depending on the number of I/O channels that tester
16
can handle, and the number of connections needed for a single chip, a certain number of chips may be tested in parallel as described above. To verify the functionality of memory arrays on the chips, tester
16
writes a specific pattern to the memory, reads the data back from the array and compares the original data pattern with the data read from the memory chip. Any discrepancies are reported and used to determine pass/fail criteria for the memory chips (if no module level redundancy is available), and in the case of wafer testing, a bit fail map is generated. In one example, a ×32 memory chip, 32 I/O channels are needed for communication between each memory chip
14
and tester
16
.
Therefore, a need exists for an apparatus for testing memory cells to both reduce costs of testing and reduce test time. A further need exists for an apparatus which reduces the number of channels needed to test each chip.
SUMMARY OF THE INVENTION
A semiconductor memory chip, in accordance with the present invention, includes a memory array including memory components to be tested. A pattern generator provides reference data to be input to and stored in the memory array. A comparator is formed on the memory chip for comparing the reference data from the pattern generator and the stored data from the memory array. The comparator further includes logic circuitry for comparing the reference data to the stored data from the memory array to provide a compare result having a matched state if the stored data matches the reference data and otherwise an unmatched state. A plurality of latches are included for receiving the compare result from the logic circuitry, the latches having a first state associated with the matched state wherein the first state is altered to a second state if the unmatched state is received from the logic circuitry. A register for storing and outputting the first and second states of the latches to provide a test result is also included.
Another semiconductor memory chip includes a memory array including memory components to be tested and redundancies for replacement of defective memory components, the redundancies each including a set of components. A pattern generator is included for providing reference data to be input to and stored in the memory array, and a comparator is formed on the memory chip for comparing the reference data from the pattern generator and the stored data from the memory array. The comparator further includes logic circuitry for comparing the reference data set to the stored data from the memory array to provide compare results having a matched state if the stored data matches the reference data and otherwise an unmatched state. A multiplexer stage is included for receiving the compare results and compressing the compare results to provide redundancy compatible data compression such that any unmatched state associated with any components of a set of components permits replacement with a redundancy of the same size as the set of components. A plurality of latches receives the compare results from the multiplexer stage, the latches having a first state associated with the matched state wherein the first state is altered to a second state if the unmatched state is received from the logic circuitry. A register is also include for storing and outputting the first and second states of the latches to provide a test result.
A DRAM memory chip in accordance with the present invention includes a memory array including memory components to be tested and redundancies for replacement of defective memory components, the redundancies each including a set of components. A pattern generator is included on the memory chip for providing reference data to be input to and stored in the memory array, and a comparator is formed on the memory chip for comparing the reference data set from the pattern generator and the stored data from the memory array, the comparator being coupled to read/write data lines of the memory array for retrieving the stored data from the memory array. The comparator further includes logic circuitry for comparing the reference data set to the stored data from the memory array to provide compare results having a matched state if the stored data matches the reference data and otherwise an unmatched state. A synchronization stage is included for synchronizing compare results output from the logic circuitry. A multiplexer stage receives the compare results associated with each memory component and compresses the compare results for each memory component to provide redundancy compatible data compression such that any unmatched state associated with any components of a set of components permits replacement with a redundancy of the same size as the set of components. A plurality of latches is included for receiving the compare results from the multiplexer stage. The latches have a first state associated with the matched state wherein the first state is altered to a second state if the unmatched state is received from the logic circuitry. A shift register is included for storing and outputting the first and second states of the latches to provide a test result.
In alternate embodiments of the present invention, the logic circuitry preferably includes one of an exclusive or gate and an exclusi
Chase Shelly A
DeCady Albert
Infineon - Technologies AG
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