On-chip circuit for transition delay fault test pattern...

Details On-chip circuit for transition delay fault test pattern... On-chip circuit for transition delay fault test pattern...

2007-11-14

2009-12-29

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

C714S731000, C713S500000

Reexamination Certificate

active

07640461

ABSTRACT:
A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.

REFERENCES:
patent: 6877123 (2005-04-01), Johnston et al.
patent: 7202656 (2007-04-01), Gearhardt et al.
patent: 7334172 (2008-02-01), Howard et al.
patent: 7558998 (2009-07-01), Watanabe

Affiliated with

Also associated with

Rating

On-chip circuit for transition delay fault test pattern... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with On-chip circuit for transition delay fault test pattern..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-chip circuit for transition delay fault test pattern... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4141359