Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-01
2001-07-10
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06260166
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to computer systems and more specifically to testing of very large integrated circuits (ICs) which cannot be easily tested from associated external electrical contact pins or wafer probes.
As it is known in the art, ICs can include a number of circuits typically containing many transistors and other electronic devices interconnected by conductive paths arranged in different circuit configurations. Those circuits can be coupled to electrical devices external to the IC via electrical contact pins that carry input and output signals to and from the device.
A portion of the above mentioned ICs are located “functionally close” to one of the electrical contact pins. After an IC is manufactured, it is tested for defects by monitoring the manner in which those contact pins respond to patterns of electrical signals, referred to as “test vectors”, that are input to the IC. Those test vectors cause the circuits to generate deterministic output values which are output on the associated contact pins. Those responses are compared with “known good values”, i.e. accurate expected values, to determine if the circuit is operating correctly. Such a test methodology becomes increasingly ineffective as ICs become larger and more circuit portions are placed functionally further away from the electrical contact pins.
A majority of the circuits that comprise an IC are typically located functionally distant from a contact pin and therefore cannot be tested effectively in the manner described above. The term “functionally distant” means that any defects present in that circuit cannot easily be determined by monitoring the associated external contact pins. For example a circuit which is functionally distant from a given contact pin may be coupled to an associated contact pin through other circuits, and may induce the same electrical signal on that contact pin whether or not it is functioning properly. Accordingly, it is essential to employ other suitable methods to test the functioning of those individual circuits.
Each time an IC is tested, a series of test vectors are imposed on its contact pins. These test vectors are typically designed to exercise a particular function involving a selected group of circuits in the IC device under test, referred to as the “DUT”. By imposing a number of test vectors on the DUT, every significant function of the device can be exercised to determine whether it is operating properly.
Typically, dedicated testing circuits are designed into the IC for monitoring these functionally distant circuits during such an IC test. Those testing circuits are typically Linear Feedback Shift Registers (LFSRs) which sample an electrical node or group of electrical nodes of a pre-selected circuit at a series of selected times during the test. Those samples are compressed into a compact representation within the LFSR. The output of the compression operation is referred to as a “segment signature”. The segment signature is serially output to an external contact pin such that it can be compared with a known good segment signature value by the IC tester. Alternatively, the samples can be stored in an uncompressed format which is output to a contact pin for cycle-by-cycle analysis, as will be described below.
Typically, many LFSRs are designed into an IC since a majority of circuits to be tested in an IC are functionally distant from a contact pin. The LFSRs are often connected in series such that the serial output of one LFSR is connected to the serial input of the next LFSR. The serial input of the first LFSR in the series and the serial output of last LFSR in the series are connected to external contact pins. When all of the LFSRs in the series have finished sampling data from the circuits to which they are coupled, they are commanded to serially shift the generated segment signatures towards the contact pin. Because the LFSRs are connected serially, a segment signature that is shifted out of a first LFSR is shifted into a second LFSR to which it is connected. The segment signature values are shifted through the serial chain of LFSRs until the entire segment signature generated by the first LFSR is shifted out of the last LFSR, i.e. onto the contact pin and into the IC tester. The segment signatures that are shifted onto the external contact pin are collectively referred to as the “signature” of the test. If the signature is not exactly the same as to a known good signature, the test fails and the circuit contains a defect that has rendered the device inoperable or merely partially operable (i.e., performing below an acceptability threshold).
When a failure is detected in a device under test (referred to as a DUT), the cause of that failure must be identified for the purpose of determining if there is a problem with the manufacturing process or whether there is an error in the design of the circuit. In either case, there are typically three procedures that are used in the industry to identify the cause of a failing test. Each of the three procedures requires significant amounts of testing time to isolate the source of the failure.
The first procedure involves operating the LFSRs in a “snap-shot” mode. In such a snap-shot mode, the LFSRs are configured to capture data during only a single specified “clock-cycle” of the test. The test vectors are imposed upon the DUT at a rate of one test vector per clock cycle. Because an IC test may typically include several million clock-cycles, such a testing methodology demands running the entire test several million times and, each time, capturing data during a different clock-cycle. The result of the test exhaustively depicts the value of the sampled signals at each cycle of the test. The error condition is subsequently determined by identifying the clock-cycle in which the sampled values differ from the known good values. This method requires a significant investment of time.
The second testing methodology used in the industry includes a “binary search.” Such a methodology divides the test vectors into two groups, each containing about half of the test vectors. A known good signature is determined for the first group of test vectors by simulating the operation of the circuit using one of many simulation methods typically used in the industry. Subsequently, the first group of test vectors is imposed on the DUT and the signature generated by the LFSRs is compared with the known good signature. If the comparison indicates that the two signatures are not identical, then the failing condition is identified as being caused by the first group of test vectors. If, on the other hand, the comparison indicates that the two signatures are identical, the failing condition is identified as being caused by the second group of test vectors. The group of test vectors in which the failing condition is found to arise is further divided into two groups and the process repeated. The test vector groups continue to be divided, and the test re-run, until the exact location of the failure is identified.
The third methodology uses a variation of the binary search method of the second test methodology to isolate the cause of the test failure to within a small predetermined number of test vectors that can be analyzed in a reasonable amount of time. The binary search method is used to identify the general location of the test vector causing the failure. The test is modified such that it will pause when it reaches the test vector area containing the failure. The LFSRs are subsequently placed into the snap-shot mode of the first test methodology and the test is restarted from the beginning. The snap shot methodology is executed from the point at which the test is paused, requiring the remaining test vectors to be repeatedly imposed upon the DUT until each cycle of the identified test vector area have been sampled.
Each of the three testing methodologies described above involve substantial pattern development effort, testing time and sampled data comparison time. Such efforts are expensive, time consuming, complex and re
Bhavsar Dilip Kantilal
Gowan Michael Karl
Compaq Computer Corporation
De'cady Albert
Hamilton Brook Smith & Reynolds P.C.
Lamarre Guy
LandOfFree
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