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MB810 encoder/decoder, dual mode encoder/decoder, and MB810...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Means for testing dynamic integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Means scanning scan path parts sequentially and capturing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Means scanning scan path parts sequentially and capturing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Measurement circuit and method for serially merging...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Measurement of health statistics for a high-speed interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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Measuring an error rate in a communication link

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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Measuring bridge-fault coverage for test patterns within...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Measuring microprocessor susceptibility to internal noise...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Measuring propagation delays of programmable logic devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mechanism and display for boundary-scan debugging information

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mechanism for decoding linearly-shifted codes to facilitate...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Mechanism for enabling compliance with the IEEE standard...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mechanism for enabling compliance with the IEEE standard...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mechanism for implementing redundancy to mask failing SRAM

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Mechanism for implementing redundancy to mask failing SRAM

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Mechanism for turbo decoding when CRC for partial blocks is...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Mechanism handling race conditions in FRC-enabled processors

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mechanism to enhance observability of integrated circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mechanism to provide test access to third-party macro...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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