Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-07-31
2010-06-08
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S732000, C714S725000
Reexamination Certificate
active
07734968
ABSTRACT:
Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuits). Basically, a shift/interface system is coupled between the FPGAs and the ASIC. During normal operation, the shift/interface system electrically couples the FPGAs to the ASIC. During the testing of the FPGAs, the shift/interface system scans in FPGA test data in series, then feeds the FPGA test data to the FPGAs, then receives FPGA response data from the FPGAs, and then scans out the FPGA response data in series. During the testing of the ASIC, the shift/interface system scans in ASIC test data in series, then feeds the ASIC test data to the ASIC, then receives ASIC response data from the ASIC, and then scans out the ASIC response data in series.
REFERENCES:
patent: 4878209 (1989-10-01), Bassett et al.
patent: 5331571 (1994-07-01), Aronoff et al.
patent: 5392297 (1995-02-01), Bell et al.
patent: 5663965 (1997-09-01), Seymour
patent: 5668817 (1997-09-01), Adham
patent: 5790561 (1998-08-01), Borden et al.
patent: 5799021 (1998-08-01), Gheewala
patent: 5844917 (1998-12-01), Salem et al.
patent: 5968190 (1999-10-01), Knaack
patent: 5973976 (1999-10-01), Sato
patent: 6020755 (2000-02-01), Andrews et al.
patent: 6249889 (2001-06-01), Rajsuman et al.
patent: 6311299 (2001-10-01), Bunker
patent: 6438722 (2002-08-01), Bailey et al.
patent: 6744274 (2004-06-01), Arnold et al.
patent: 6944836 (2005-09-01), Lai
patent: 7047464 (2006-05-01), Bailis et al.
patent: 7308630 (2007-12-01), Grupp et al.
Savkar, A.D.; N-Way Testpoint for Complex LSI Design; IBM Technical Disclosure Bulletin, vol. 14, No. 10, Mar. 1972; pp. 2937-2938.
Pruden et al.; Specification of device isolation requirements by operation; IBM Technical Disclosure Bulletin, vol. 28, No. 3, Aug. 1985; 2 pages.
Grupp Richard J.
Ockunzzi Kelly A.
Taylor Mark R.
International Business Machines - Corporation
Kerveros James C
LeStrange Michael J.
Schmeiser Olsen & Watts
LandOfFree
Mechanism to provide test access to third-party macro... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mechanism to provide test access to third-party macro..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mechanism to provide test access to third-party macro... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4197472