Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2002-06-27
2003-05-06
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
06560739
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates generally to testing integrated circuits (ICs), and more particularly to testing according to the Institute of Electrical and Electronics Engineers (IEEE) standard 1149.1.
2. Discussion of Background Art
Testing of integrated circuit devices or components is facilitated by providing each input and output (I/O) pin of the devices with a boundary-scan cell which enables using boundary-scan techniques to control and observe signals at the device boundaries. The IEEE standard 1149.1 specifies a boundary-scan architecture and a protocol which defines test logic that can be used with ICs in a standardized approach to testing the IC and interconnections between IC components when assembled on a printed circuit board or other substrate to form a product. The IEEE standard 1149.1 also allows observing or modifying circuit activity during otherwise normal operation of the circuit. Additionally, the defined test logic can access other design-for-test features built into a device (IEEE standard 1149.1 - 1990, pages 1—1 and 1-5). The standard is intended to confirm 1) that each device or component performs its required function, 2) that components are interconnected correctly, and 3) that components interact correctly and that the product performs its intended function.
In general, the test circuitry defined by the standard allows feeding test instructions and associated test data into a component, and subsequently allows reading out results of the execution of such instructions. All instructions, test data, and test results are communicated in a serial format. Starting from an initial state in which the defined test circuitry is inactive, a typical test sequence is as follows: 1) serially load the component with the instruction codes for the particular test to be performed, 2) execute the selected test and 3) shift data out of the component to or through the bus master and examine test results (Id., pages 1-2).
FIG. 1
shows a conventional scan cell
100
, including two multiplexers
102
and
108
, a capture cell
104
, and an update cell
106
. Input signals to cell
100
include signal_input, serial_input, shift_dr, shift_clk, update_clk and mode. Output signals include signal_output and serial_output. Depending on the control signals (shift_dr and mode) applied to lines
1014
and
1016
to multiplexers
102
and
108
, data (signal_input) can be either loaded through lines
1003
and
1004
into capture cell
104
or driven through line
1006
and multiplexer
108
to signal output on line
1012
. Signals which have arrived through lines
1003
,
1004
, and
1008
are held by update cell
106
at line
1010
while new serial input data is shifted through lines
1002
,
1004
, and
1008
to the serial output of cell
100
and on to the serial_input of another cell
100
(not shown).
FIG. 2
shows an example of three prior art connected scan cells
100
A,
100
B, and
100
C to illustrate how data is shifted and output for observations. The cell
100
A serial output line
1008
A is connected to the cell
100
B serial input line
1002
B. Similarly, the cell
100
B serial_output line
1008
B is connected to the cell
100
C serial_input line
1002
C. Cells
100
A,
100
B, and
100
C have update_clk and shift_clk signals connected together (not shown). Appropriate control signals applied to multiplexers
102
and clocking signals applied to capture cells
104
will shift serial data input from serial input line
1002
A of cell
100
A to lines
1008
A,
1008
B, and
1008
C. When ready for observation, the data on lines
1008
A,
1008
B, and
1008
C are clocked through the respective flip-flops
106
A,
106
B, and
106
C to lines
1010
A,
1010
B, and
1010
C to appear on lines
1012
A,
1012
B, and
1012
C, respectively.
FIG. 3
shows a prior art device
300
complying with the IEEE standard 1149.1. Device
300
includes an IEEE standard 1149.1 Test Access Port (TAP) controller
306
, and multiple scan cells
100
, each associated with an input, output or I/O pin
302
, interconnected to form a shift register chain around the border of the core logic
304
. TAP controller
306
is a synchronous state machine and a general-purpose port that, in conjunction with boundary scan cells
100
and through five signals Test Clock (TCK), Test Reset Input (TRST), Test Mode Select (TMS), Test Data Input (TDI) and Test Data Output (TDO), provides signals and access to support the IEEE standard 1149.1 boundary-scan functions. Signal TDI provides test instructions and data. Signal TDO provides the serial output of test instructions and data. Signal TRST provides for asynchronous initialization of TAP controller
306
. Signals TCK and TMS cause TAP controller
306
to control the sequence of operations of the defined test circuitry, and to generate clock and control signals as needed for the instruction and test data and for other parts of the test logic architecture. The IEEE standard 1149.1 describes signals TCK, TRST, TMS, TDI, and TDO in detail.
The boundary scan chain comprising cells
100
receives serial input signal TDI at the serial_input (
FIG. 1
) terminal and produces output signal TDO at the serial_output terminal. Signals TMS, TRST, and TCK through TAP controller
306
, generate the other
FIG. 1
signals (shift_clk, update_clk, shift_dr, and mode).
FIGS. 4A-C
show prior art examples of different interconnections of multiple scan devices
100
that comply with the IEEE standard 1149.1.
FIG. 4A
shows a serial connection of devices
100
using one TMS and one TCK signal;
FIG. 4B
shows devices
100
connected in series in two chains connected in parallel using two TMS signals and a TCK signal; and
FIG. 4C
shows multiple independent paths using common TMS and TCK signals.
The IEEEE standard 1149.1 (1994) defines a Boundary-Scan Description Language (BSDL) for describing testing information, which is input to an automated process with little or no manual interaction for generating a test program.
Objectionably, multiplexer
108
in scan cell
100
(
FIG. 1
) causes undesirable propagation delay in the functional signal path, especially in high-speed (above 200 Mhz clock) or timing-critical Application-Specific Integrated Circuit (ASIC) devices. Various solutions have emerged to deal with high-speed boundary-scan designs. One solution uses performance-optimized “hard macros,” or commonly used logic design functional blocks, in boundary scan cells. The hard macros are constituted of logic elements (AND OR gates, etc.) that are physically close to one another and permit short connecting line delays. However, ASIC designers in many cases do not have access to the desired hard macros, and creating these hard macros requires additional time, resources, and indepth knowledge of a device technology.
Instead of hard macros, ASIC designers can use a standard ASIC library of a vendor's logic components in a “soft macro” approach to synthesize boundary-scan cells. However, this software synthesis approach adds routing delay between “soft macro” components, introduces, in the boundary-scan cells, longer overall delay than the “hard macro” approach, and causes additional delay in the critical signal path, thereby encountering the same problem that is supposed to be solved. Consequently, this software approach is unacceptable for high-speed designs. Additionally, meeting the requirements of the boundary-scan standard in timing-critical and high-speed ASIC designs may be impractical because design time, resources, and device performance overhead costs are too high.
Another solution to testing high speed ASICs omits certain signals and/or functions of the boundary-scan standard in order to reduce performance overhead. However, this solution leaves “holes” or incomplete pin fault coverage for a Device Under Test (DUT). In cases where there is a need to test the uncovered pins, it is often impossible to add non-boundary scan-based test vectors to test those pins.
Another approach leaves to test engineers the problem of modifying test v
Cisco Technology Inc.
Hanish Marc S.
Moise Emmanuel L.
Thelen Reid & Priest LLP
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