Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-10-10
2006-10-10
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
07120842
ABSTRACT:
A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are monitored during the burn-in tests to provide a mechanism for observing selective scan chain outputs and memory BIST status outputs.
REFERENCES:
patent: 6535440 (2003-03-01), Lim et al.
patent: 6675338 (2004-01-01), Golshan
patent: 6950974 (2005-09-01), Wohl et al.
patent: 2003/0149913 (2003-08-01), Balachandran et al.
patent: 2003/0167426 (2003-09-01), Slobodnik
Agashe Anupama Aniruddha
Barevadia Gordhan
Krishnamoorthy Nikila
Parekhji Rubin Ajit
Simpson Neil J.
Brady W. James
Chung Phung My
Shaw Steven A.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Mechanism to enhance observability of integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mechanism to enhance observability of integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mechanism to enhance observability of integrated circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3699947