Mechanism for implementing redundancy to mask failing SRAM

Details Mechanism for implementing redundancy to mask failing SRAM Mechanism for implementing redundancy to mask failing SRAM

2008-03-18

2008-03-18

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S723000, C365S201000

Reexamination Certificate

active

11096978

ABSTRACT:
In some embodiments, an apparatus to implement redundancy for failure masking in memory is disclosed. The apparatus comprises a built-in self test (BIST) log to store BIST data representing faulty columns of a memory, a redundancy configuration logic to generate one or more select signals based on the BIST data, an input shifter to map input data to one or more redundant columns of the memory, based on the one or more select signals, to avoid the faulty columns, and an output shifter to map output data from the one or more redundant columns of the memory, based on the one or more select signals, by bypassing the faulty columns. In one embodiment the memory is a static random access memory (SRAM). Other embodiments are also described.

REFERENCES:
patent: 5758056 (1998-05-01), Barr
patent: 6182257 (2001-01-01), Gillingham
patent: 6243307 (2001-06-01), Kawagoe
patent: 6732229 (2004-05-01), Leung et al.
patent: 2005/0240838 (2005-10-01), Iwai

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